1. Field of the Invention
This invention relates to computers and more particularly to integrating a dynamic random access memory (DRAM) controller onto a microcontroller.
2. Description of the Related Art
Controllers for DRAMs are known in the art. In microcontrollers, various level of support for DRAMs has been provided. For example, the AM186.TM.ES microcontroller provides support logic for refresh. Refreshing DRAMs is necessary to maintain the integrity of the DRAM contents, as is known in the art. However, DRAMs also typically require the address bus to be mulitplexed between rows and columns and require row and column address strobes (RAS and CAS), respectively indicating the presence of the row and column address on the bus. While prior art processors may include DRAM controllers, integrating a DRAM controller onto an existing microcontroller architecture that did not previously provide DRAM support can cause problems in, e.g., maintaining pin compatability with the existing microcontroller design. In the AM186.TM.ES microcontroller, DRAM support logic external to the microcontroller is still required to provide, e.g., RAS/CAS signals and multiplexed address bits to the DRAM. Externally provided DRAM control logic requires additional parts and space. Further, externally provided DRAM support logic can result in slower access time to the DRAMs. Such slower access time can be accommodated by incorporating wait states into the bus cycles to give the external device time to, e.g., provide requested data. For example, the AM186.TM.ES processor must insert wait states for DRAM access when the externally supplied clock speed of the microcontroller is, e.g., 40 MHz.